Xi Wang, Yiwen Zhong, Hongbin Pu,†, Jichao Hu, Xianfeng Feng, and Guowen Yang

1Department of Electronic Engineering, Xi'an University of Technology, Xi'an 710048, China

2Xi’an Key Laboratory of power Electronic Devices and High Efficiency Power Conversion, Xi’an 710048, China

3Sanli Intelligent Electric Co., Ltd, Xi’an 712000, China

Abstract: Lateral current spreading in the 4H-SiC Schottky barrier diode (SBD) chip is investigated. The 4H-SiC SBD chips with the same vertical parameters are simulated and fabricated. The results indicate that there is a fixed spreading resistance at onstate in current spreading region for a specific chip. The linear specific spreading resistance at the on-state is calculated to be 8.6 Ω/cm in the fabricated chips. The proportion of the lateral spreading current in total forward current (Psp) is related to anode voltage and the chip area. Psp is increased with the increase in the anode voltage during initial on-state and then tends to a stable value. The stable values of Psp of the two fabricated chips are 32% and 54%. Combined with theoretical analysis, the proportion of the terminal region and scribing trench in a whole chip (Ksp) is also calculated and compared with Psp. The Ksp values of the two fabricated chips are calculated to be 31.94% and 57.75%. The values of Ksp and Psp are close with each other in a specific chip. The calculated Ksp can be used to predict that when the chip area of SiC SBD becomes larger than 0.5 cm2, the value of Psp would be lower than 10%.

Key words: 4H-SiC; Schottky barrier diode; lateral spreading current

1. Introduction

Silicon carbide (SiC) has proved to be one of the most promising wide band gap semiconductor materials for high power electronic devices[1,2]. Nowadays, with the development of large wafer-size and high-quality epitaxial technology, SiC power devices have exhibited a trend of rapid development[3-6]. The 4H-SiC Schottky barrier diode (SBD) is the first commercial power device of SiC that has shown significant advantages compared with silicon (Si) fast recovery diodes (FRDs)[7,8]. In recent years, the applications of SiC SBDs have increased and the research on 4H-SiC SBDs have made significant achievements[9-12]. Moreover, the 4H-SiC SBDs have become the most commercial devices among the SiC power devices[13,14].

To reduce costs, the area of the 4H-SiC SBD chip has been scaled down by minimizing the resistance of the active area and narrowing down the length of the terminal[12,15]. Besides contributions for the blocking voltage, the terminal region also contributes to the total forward current through the lateral spreading current[16]. Nevertheless, there are fewer studies about current spreading at the terminal region of the 4H-SiC SBD chips[16]. Investigation of lateral current spreading at the terminal region would be significant for decreasing the chip area of 4H-SiC SBD chips. Moreover, the results may also help reduce the costs of other SiC power devices.

In this paper, 4H-SiC SBD chips with a field limiting ring(FLR) terminal are simulated and fabricated. The lateral current spreading in the 4H-SiC SBD chip is investigated and calculated. Moreover, the effect of the lateral current spreading on the forward performance of the device is discussed and analyzed.

2. Simulation

To investigate the lateral spreading current in the 4H-SiC SBDs, simulations are carried out using Silvaco TCAD tools.Table 1 lists the physical models and the parameters, including the bandgap energy model[17], the incomplete ionization model[18], the mobility model[19], the impact ionization model[20], and the Schottky contact model[21]. The schematics of the device structures and the parameters used in the simulation are shown in Fig. 1. As shown in Fig. 1(a), the terminal region consisted of field limiting rings and scribing lines are in-cluded in the structural model to simulate the lateral spreading current. The width of the active and the terminal regions in Fig. 1(a) areWand 175μm, respectively. A structural model without the terminal region is also constructed to extract lateral spreading current as shown in Fig. 1(b).

Table 1. Models and parameters used in the simulation.

Fig. 1. (Color online) Schematics of the device structures used in the simulation. (a) Considering the lateral spreading current. (b) Ignoring the lateral spreading current.

Fig. 2. Simulated relationship between chip size and proportion of spread current in the total forward current.

Because the terminal region is included, the forward current of the structure model shown in Fig. 1(a) contains the lateral spreading current. However, the forward current of the structure model shown in Fig. 1(b) does not contain the lateral spreading current. Therefore, proportions of lateral spreading current in the total forward current (Psp) of the devices are extracted through simulation. The values ofWand the corresponding chip sizes in the simulation range from 0.325 to 3.325 mm and from 1.0 to 49 mm2, respectively. The simulated relationship betweenPspandSis shown in Fig. 2. With the increase in the chip size from 1.0 to 49 mm2,Pspis decreased from 53% to 8%. The simulation results indicate that the valuePspdecreases when the SBD chip becomes larger.

3. Experiment

Fig. 3. (Color online) Top view of the fabricated SiC SBD chip.

To further investigate the lateral spreading current, 4HSiC SBD chips with the same terminal structure are fabricated on a 4-inch 4ooff-axis N-type 4H-SiC epitaxial wafer bought from TYSiC Inc. The thickness of the epitaxial layer and the substrate are 7.0 and 350μm, respectively. There is a 0.5μm highly doped epitaxial buffer layer between the drift region and the substrate. The doping concentrations of the drift and the buffer layers are 1.0 × 1016and 1 × 1018cm-3, respectively. The FLRs are formed by Al implantation and followed by 1700 °C high-temperature annealing processes, where SiO2is used as a masking film during the implantation process. A carbon film made by carbonized photoresist is used to protect the 4H-SiC during the high-temperature annealing process. After the annealing process, the carbon film is removed through sacrificial oxidation. Ni, used as the ohmic contact metal, is deposited on the bottom by evaporation equipment. After deposition, a rapid thermal process (RTP) at 1000 °C is carried out to form the ohmic contact.Then, Ni is deposited on the top through the lift-off process and the Schottky contact is formed after RTP. Ag and Al are used as the cathode and anode pads, respectively. Finally,the devices are passivated by SiO2and polyimide (PI). The chip sizes (S) are 2.0 × 2.0 mm2and 1.0 × 1.0 mm2. The sizes of the active areas (SA) in the two chips are 1.65 × 1.65 mm2and 0.65 × 0.65 mm2. Fig. 3 shows the top view of the fabricated SiC SBD chip. It can be seen from the figure that after scribing, the width of the terminal region and scribing trench region is 175μm.

After the fabrication processes, the Keysight B1505A power device test system is used to test the SBD chips. The forward and the reverse current-voltage curves of the two chips are shown in Fig. 4. The turn-on voltage of the fabricated SiC SBD chip is about 0.9 V. When the anode voltage is 1.55 V,the forward current of the two SBD chips are 10.7 and 2.5 A.The values of the on-state resistance of the two chips are calculated to be about 145 and 620 mΩ. When the cathode voltage is 650 V, the reverse leakage currents of the two chips are 1.07 and 0.17μA. Since the chip sizes are different,the forward current (IF) and the leakage current (IR) between the two SBD chips are different. The SBD with a larger chip size shows higher current values.

Fig. 4. (Color online) Current-voltage curves of the fabricated SBD chips. (a) Forward current-voltage curves. (b) Reverse current-voltage curves.

Fig. 5. (Color online) Current density-voltage curves of the fabricated SBD chips. (a) Forward current density-voltage curves. (b) IF/SA-voltage curves. (c) Reverse current density-voltage curves. (d) IR/SA-voltage curves.

4. Analysis and discussion

Fig. 5 shows the current density-voltage curves of the fabricated SBD chips. Although the vertical parameters and the fabrication processes are the same, both forward current densities (JF=IF/S) and reverse current densities (JR=IR/S)between the two chips are different. Figs. 5(a) and 5(c) show that the SBD with a larger chip size shows higher forward and reverse current densities. In Figs. 5(b) and 5(d) , the current densities are expressed usingSAas respectively. The calculated forward current density (JFA) in the SBD with a smaller chip size is higher. Meanwhile, the calculated reverse current densities (JRA) in the two SBD chips are almost the same. The different results may be caused by the lateral spreading current in the terminal region. When calculating the current densities usingSA, the conduction area in the terminal region is ignored. However, the contribution of the conduction area in the terminal region on the forward current is included. Therefore, the SBD with a smaller chip size shows a higher forward calculated value. Meanwhile, the reverse calculated value is almost the same as shown in Fig. 5(d). It is because the reverse leakage current is very small and there is almost no lateral spreading during the reverse biased condition. Although, the current density calculating method that usesSAis incorrect in analyzing the SiC SBD chips, the method is useful for analyzing the lateral spreading current.

Fig. 6. (Color online) Schematic diagrams of the lateral current spreading in the 4H-SiC SBD chip. (a) Cross-section view. (b) Vertical view.

Fig. 6 shows the schematic diagrams of the lateral current spreading in the 4H-SiC SBD chips. In the 4H-SiC SBD chip, the entire bottom is covered by a cathode electrode, at the same time, the anode electrode area at the top is depending on the active area. As a result, the top anode electrode and the bottom cathode electrode in the 4H-SiC SBD chip are asymmetrical. Therefore, there are potential and electron density differences at the edge of the active area in the 4H-SiC SBD at on-state. The potential and the electron density differences cause the lateral transport of electrons. The lateral transport of electrons leads to spreading current at the terminal region of the active area. Then, according to the current flowing path, the total forward current (IF) can be divided into two portions. One is the current that flows through the active area and the other is the current that flows through the spreading area under the terminal region. Therefore, the total forward current (IF) of the SBD chip can be defined as the sum of two portions:

whereIAandIspare the currents that flow through the active and the terminal regions, respectively.

SinceIFconsists ofIAandIsp, a new equation can be achieved by substituting Eq. (3) into Eq. (1)

If the process deviation during the fabrication is ignored, the current density that flows through the active region is a fixed value. Then,IA/SAin the two SBD chips should be the same.SubtractingJFA1of the larger SBD chip fromJFA2of the smaller SBD chip, the result can be written as:

whereIsp1andSA1are the spreading current and the active area in the SBD chip with larger size, respectively. WhileIsp2andSA2are the spreading current and the active area in the SBD chip with smaller size, respectively. The values ofSA1andSA2in this work are 0.027225 and 0.004225 cm2, respectively.

In order to further analyze the lateral spreading current in the 4H-SiC SBD chip, a new parameter needs to be defined to describe the contribution of the spreading current along the edge around the active area. Since the total spreading currentIspis a sum of the extended currents in each region along the active boundary, the linear density of the lateral spreading current along the active boundary (Jsp) is defined in the SBD chips. Thus, the total spreading current in the SBD chip can be expressed as the product ofJspand the length of the active boundary. The length of the active boundary is scilicet the perimeter of the active area. Considering the vertical parameters, the terminal structure and the fabrication process are all the same in the two SBD chips, andJspin the two SBD chips can be approximately equal[22,23]. Then Eq. (5) can be written as:

Fig. 7. (Color online) Calculated Jsp and Psp at different anode voltages of the SBD chips.

whereCA1andCA2are the perimeters of the active area in the two 4H-SiC SBD chips. The values ofCA1andCA2in this paper are 0.66 and 0.26 cm, respectively. Then, from Eqs. (1)and (6),Jspcan be written as:

Then, the value ofIspand the proportion ofIspin the total forward current (Psp) of the SBD chip can be calculated as:

and

Fig. 8. Ksp-S curve and Psp of the fabricated SBD chips.

respectively. According to Eqs. (8) and (9),JspandPspof the fabricated SiC SBD chips at different anode voltages are calculated and shown in Fig. 7. The calculatedJspexhibits a linear relation with the anode voltage, indicating that there is a fixed spreading resistance at the on-state in the current spreading region. Therefore, the linear specific spreading resistance in the current spreading region at the on-state can be calculated through theJspcurve in Fig. 7. The calculated value of linear specific spreading resistance is about 8.6 Ω/cm. Even though the spreading resistance is fixed for a specific chip,thePspis still increased with the increase in the anode voltage during the initial on-state. Once the anode voltage becomes higher, the increasing rate ofPspslows down andPsptends to a stable value. As shown in Fig. 7,Pspin the two fabricated chips tends to be stable at the forward voltage drops of 1.5 and 1.55 V with stable values of about 54% and 32%, respectively.

For SiC SBDs with different chip sizes, the proportions of the active area in the entire chips are different. The expected active area, the terminal region and the scribing trench also occupy a certain proportion in the entire chip. The proportions of the terminal region and the scribing trench in the entire chip may be concerned with the lateral spreading current.Therefore,Kspis defined as the proportion of the terminal region and the scribing trench in the entire chip in this work.ThenKspcan be calculated as:

whereSAandSare the active and the chip areas, respectively. According to Eq. (10),Kspfor SiC SBDs with different chip sizes can be theoretically calculated assuming that these SBD chips have the same vertical parameters, the same terminal structures and the same fabrication processes. The relation curve of calculatedKspandSfor SiC SBDs with different chip sizes is shown in Fig. 8. It can be seen from the figure that when the size of the SiC SBD chip is small, the active area is small and the proportion of terminal and scribing trench is large. With the increase in the chip size,Kspdecreases. Fig. 8 shows thatKspis lower than 20% when the chip area is larger than 0.1 cm2. The values ofPspof the simulated SBD chips and the fabricated SBD chips are also calculated and marked in Fig. 8. It is clear that not all the terminal regions and the scribing trenches are effectively contributed to the lateral spreading current. Therefore, there is a relation coefficient betweenPspandKsp. The markedPspcomparatively coincides with theKspcurve. In the SiC SBDs with chip sizes of 2.0 × 2.0 mm2and 1.0 × 1.0 mm2, the calculated values ofKspare 31.94% and 57.75%, respectively. Comparing the calculatedKspandPspin the two chips, the values are closed in each chip. For the SBD chip with a chip size of 2.0 × 2.0 mm2,the calculatedPspis slightly higher thanKsp. Meanwhile, for the SBD chip with a chip size of 1.0 × 1.0 mm2, the calculatedPspis slightly lower thanKsp. The difference between the calculatedPspandKspmay be caused by process deviation during the fabrication and relation coefficient betweenPspandKsp. According toKsp-Scurve, it can be predicted that when the chip area of the fabricated SiC SBD becomes larger than 0.1 cm2, the value ofPspwould be lower than 20%.When the chip area of the fabricated SiC SBD becomes larger than 0.5 cm2, the value ofPspwould be lower than 10%.

5. Conclusion

In this paper, the lateral current spreading in the 4H-SiC SBD chip is investigated through simulation and experiment.The obtained results indicate that there is a fixed spreading resistance at the on-state in the current spreading region. The linear specific spreading resistance at the on-state is calculated to be about 8.6 Ω/cm in the fabricated chips. Moreover, the proportion of the lateral spreading current in the total forward current (Psp) is related to both the anode voltage and chip area. During the initial on-state,Pspincreases with the increase in the anode voltage. ThenPsptends to a stable value.The stable values ofPspof the two fabricated chips are about 32% and 54%. The calculated proportions of the terminal region and the scribing trench in the entire chip (Ksp) of the two fabricated chips are 31.94% and 57.75%, respectively,which are closed withPspin a specific chip. The calculatedKspcan be used to predictPspin the SiC SBD chips with different sizes. When the chip area of the fabricated SiC SBD becomes larger than 0.5 cm2, the value ofPspwould be lower than 10%. The results obtained in this work can be introduced to the lateral spreading current investigations in other SiC power devices.

Acknowledgements

This work was supported in part by National Natural Science Foundation of China (62004161), in part by Natural Science Basic Research Plan in Shaanxi Province of China(2020JQ-636), in part by Scientific Research Project of Education Department of Shaanxi Province (20JK0796), in part by Youth talent lift project of Xi’an Science and Technology Association (095920201318) and in part by Bidding Project of Shanxi Province (20201101017).