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具有仲裁机制的RS 485总线设计

2017-09-07李周利骆丹妮赵学敏

现代电子技术 2017年16期
关键词:信号设计

李周利 骆丹妮 赵学敏

摘 要: 为了解决普通RS 485總线中多个节点容易引发总线竞争、数据冲突和长期独占总线的问题,设计了具有总线仲裁机制的RS 485总线。在普通RS 485总线基础上增加了硬件握手和总线控制相关硬件,各个从节点能否占有总线需请求主节点给予授权;从节点按硬件连接的自然优先级排序;采用软、硬件结合方式控制各个从节点对总线的占有时间,即通信结束、软件计时或硬件定时时间到均控制硬件释放总线,避免了因某个从节点自身故障导致长期独占总线的通信错误,提高了RS 485总线的通信效率,增加了整个通信系统的可靠性和稳定性。

关键词: RS 485总线; 仲裁机制; 优先级排序; 定时总线释放

中图分类号: TN911?34; TP336 文献标识码: A 文章编号: 1004?373X(2017)16?0177?03

Abstract: In order to solve the problems that the multiple nodes in the common RS 485 bus easily lead to bus competition, data conflict and long?term exclusive bus, a RS 485 bus with arbitration mechanism was designed. Some hardwares that are related to handshaking and bus control are added to the common RS 485 bus. Each slave node requests the master node to give an authorization for making it occupies the bus, and then these slave nodes are sorted, according to the natural priority of hardware connection. Finally, a combination mode of software and hardware is used to control the occupation time of each node for the bus. In the end of communication, software or hardware timer releases the bus by controlling the hardware, which avoids the communication error that a slave node occupies the bus for a long term, which is caused by its own fault. This method can improve communication efficiency of RS 485 bus and increase the reliability and stability of the whole communication system.

Keywords: RS 485 bus; arbitration mechanism; priority ranking; timing bus release

0 引 言

RS 485总线以其结构简单、成本低廉、可选芯片多、便于维护、可靠性高等诸多优点被广泛应用于远程自动工控环境[1?3]。由于普通RS 485总线采用主从式通信方式,各从节点完全不受其他节点制约,如有两个或两个以上节点同时向总线发送数据,将会发生总线竞争,导致通信数据错误,发送失败[4];且某节点若出现通信故障,则可能出现该节点长期独占总线的情况。针对多机通信中的数据冲突问题,已有的一种解决方法是采用类似于以太网的载波监听多路访问/冲突检测协议(CSMA/CD)[5?6]。数据接收端对接收到的数据进行校验,如果出错则认为发生了总线冲突,接收端不会发送确认帧,若在规定时间内未收到确认帧,发送端就调用冲突处理函数[7]。……

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