HUANG Xiao-min, ZHANG Zhi-jie

(Key Laboratory of Instrumentation Science & Dynamic Measurement (North University of China),Ministry of Education, Taiyuan 030051， China)



Design of IP core for IIC bus controller based on FPGA

HUANG Xiao-min, ZHANG Zhi-jie

(KeyLaboratoryofInstrumentationScience&DynamicMeasurement(NorthUniversityofChina),MinistryofEducation,Taiyuan030051，China)

The intellectual property (IP) core for inter-integrated circuit (IIC) bus controller is designed using finite state machine (FSM) based on field programmable gate array (FPGA). Not only the data from AT24C02C can be read automatically after power on, but also the data from upper computer can be written into AT24C02C immediately under the control of the IIC bus controller. When it is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.

field programmable gate array (FPGA); IIC bus; intellectual property(IP) core; test system

0 Introduction

The inter-integrated circuit (IIC) bus from Philips is a simple, two-wire and synchronous serial bus. It is applicable to the communications among various serial equipment[1]. Compared with traditional parallel bus system, IIC bus system has the advantages of simple structure, good maintainability, easy extensibility and high reliability[2]. The blast wave overpressure test system needs to read and store important working parameters automatically. In this paper, an intellectuall property (IP) core for IIC bus controller is designed for data transmission automatically among a variety of serial equipment[3-4]considering that the IP core has the advantages of less resources, high flexibility, easy portability and short development cycle.

1 Working principle

1.1 AT24C02

AT24C02 belongs to electrically erasable programmable read-only memory (EEPROM) and supports IIC bus data transfer protocol. It has simple peripheral circuit, small package and low power. Especially, it is electrically erasable, therefore, it is suitable for mass storage[5]. IIC bus includes a bidirectional data wire SDA and a clock wire SCL for full duplex synchronous data transmission[6]. When IIC bus is idle, SDA and SCL must maintain keep in a high level; When IIC bus is closed, the SCL clamp in a low level. Because IIC bus interface is open drain (OD) output and open collector (OC) output, all the outputs of the bus can realize “and” logic function, which requires the output terminal of IIC bus to be connected with pull-up resistors[7]. The schematic diagram of AT24C02C is shown in Fig.1.

Fig.1 AT24C02C schematic diagram

1.2 IIC bus data transmission standard[8]

The data between upper computer and AT24C02C transmitted by IIC bus is composed of start signal, address code, a number of data bytes, response signal and stop signal. When the communication starts, the upper computer sends a start signal (when SCL is high, SDA produces a falling edge), AT24C02C address code and a read/write signal (there are 7 bytes in all from the AT24C02C address and read/write control signal R/W, where R/W=“0” indicates a write operation and R/W= “1” indicates a read operation). Then SDA is set to be a high resistance state and the upper computer waits for receiving ACK response signal (AT24C02C makes SDA low), thus the upper computer can continue to send data. When the communication is completed, the upper computer sends a stop signal. In data transmission process, when SCL is in high level, SDA must ensure the stability of the data; After transmitting each one byte data, a response signal ACK must be sent by the receiver.

With IIC bus data transmission rate of 100-400 kbps and power supply of +5 V, the input level is defined as

VILmax=1.5V,VIHmin=3V,

Withabroadsupplyvoltage,inputlevelisdefinedas

VILmax=1.5VDD,VIHmin=3VDD,

where VDD is reference voltage.

2 IP core design

IP core is an integrated circuit core with intellectual property and has repeated verification macro modules with specific functions. It has nothing to do with chip manufacturing process and can be embedded into different semiconductors. The soft core of IP core is the most widely used form. For the development of FPGA, IP core can provide abundant resources and make the design correspondingly become more convenient, therefore, IP core design has very practical value[9]. This paper describes the soft core design for IIC bus controller using finite state machine (FSM).

2.1 FSM

FSM is a general and intuitive method for digital system design. Theoretically, any complex digital design can be realized by FSM method. The state machines can be classified into two types: Moore state machine and Mealy state machine. The output of Moore state machine is a function of current input and current state; the current output of Mealy state machine is determined by its present state. This paper adopts the combination of the two types of state machines to describe the system state, of which some outputs are only related to the current state and other outputs are related to both the present state and the current input. It no only simplifies the number of the states, but also improves code universality and readability.

2.2 Implementation of soft core[10]

Based on integrated software environment (ISE) design suite 10.1 platform, the soft core for IIC bus controller is implemented for read/write control of blast wave overpressure test system . The work flow is shown in Fig.2.

Fig.2 Work flow of test system

The system clock frequency is 20 MHz, digital clock manager (DCM) module produces 1 MHz clock signal for IIC bus controller module. After power on, the system initialization starts. Before reading the working parameters from AT24C02C, the system state is set at default values. Then the sequential read mode is used to read six parameters: magnification, trigger level, sampling frequency, data storage capacity, negative delay length and sensor parameters. When the six parameters are reset again, firstly, the parameters are stored in the internal registers, and then the working parameters are output to other modules. Meanwhile, all the parameters are stored in AT24C02C by page write mode. Thus, the original parameters are refreshed. After that, the program will continually and repeatedly monitor whether there are parameters that need to be stored.

3 Experiment and analysis

3.1 Timing simulation and analysis

To verify the design accuracy of IP core, function simulation is performed in Modelsim SE 6.5.

First of all, dummy write operation is executed for initialization and the simulation waveforms are presented to write device address 10100000 and store address 00000000, as shown in Fig.3.Then IIC bus controller sends device address and read command, as shown in Fig.4. After reading the first data, the upper computer generates a response signal (ACK= “0”) , other four parameters and a stop signal. At the same time, the working parameters are refreshed, replacing initialization default parameters of the controller, as shown in Fig.5. SDA must be set in a high impedance state before the upper computer receives the response signal, otherwise the data bus will be in conflict and the upper computer can not receive the response signal from AT24C02C accurately.

Fig.3 Simulation waveform of dummy write opration

Fig.4 AT24C02C address and read

With page write mode, the initialization and dummy write operation send each one byte data and AT24C02C generates a response signal(ACK=0) . Then the internal low address automatically increases 1 and the high level remains unchanged.Five working parameters are stored in AT24C02C sequentially and a stop signal is output by IIC bus controller finally. If the parameters need to be renewed, what can be done is to repeat the above operations and update the data in AT24C02C.

After function simulation, the internal signals of FPGA are real-time read by using ChipScope Pro through joint test action group (JTAG) interface. The data read back by the computer is consistent with the working parameters, therefore, the system accuracy is high.

Fig.5 Reading last parameter and stop signal

3.2 IP core verification

Fig.6 shows the overall structure of the storage test system based on FPGA. Fig.7 is a photo of designed test system. The system uses XC3S500E Chip from Xilinx company as the core control unit and AT24C02C from Atmel company to store parameters.

Fig.6 Block diagram of test system

Fig.7 Photo of test system

Wireless storage test system mainly consists of sensors, signal conditioning circuit, analog-to-digital(A/D) conversion circuit, control circuit, storage circuit, Wi-Fi transmission circuit, universal serial bus (USB) communication circuit, as shown in Fig.6. The main working principle of the system is as follows: Based on rich logic units and input/output(I/O) ports of FPGA, the peripherals modules are controlled by FPGA orderly. The working parameters are automatically read and stored. At the same time, the system monitor information of Wi-Fi wireless module ceaselessly. When receiving the commands sent by the upper computer, the module executes the corresponding operations. If the working parameters need to be refreshed, the working parameters of the IIC bus controller will cover the storage space in AT24C02C.

Meanwhile, A/D converter does not stop data acquisition and conversion. It compares the value set before trigger to avoid false trigger. Once successively 10 points are greater than the set value, the system is regarded as being triggered. Thus, the program begins to record the data and judge whether to achieve preset storage length. In the process of data acquisition, direct memory access(DMA) module is used to send data to SDRAM quickly and efficiently. After data acquisition, A/D converter is closed and the system enters low power consumption state to wait for the arrival of read command. When the upper computer in low power consumption state sends read command, the data in SDRAM is recovered by wireless module or USB interface.

To verify the reliability of IP core, the blast tests were conducted. Before the test, the system parameters are set: magnification is two times, the sampling frequency is 2 MHz, negative delay length is 64 KB, trigger level is 1 270 mV, and data storage length is to 2 MB. The system collects and store actual blast wave signals, and the collected data is read by the upper computer through USB interface. The waveform is shown in Fig.8. The test result is close to the test standard, agreement and parameters. It indicates the reliability of the test system.

Fig.8 Blast wave overpressure test result

4 Conclusion

The IP soft core for IIC bus controller is designed using FSM method based on FPGA, which is simple and modularized. IP soft core can greatly reduce the difficulty of system design and shorten development cycle. The storage test system for blast wave overpressure has the characteristics of high speed, miniaturization, low power consumption, high interference immunity and stability. The field test validates the accuracy and reliability of IP core.

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基于FPGA的IIC总线IP核设计

黄晓敏， 张志杰

(中北大学 仪器科学与动态测试教育部重点实验室， 山西 太原 030051)

采用FSM在FPGA上设计了IIC总线控制器。 系统上电后它可自动从AT24C02C芯片中读取数据； 从上位机接收到新的数据后， 它也可自动将其存储到AT24C02C中。 该IIC总线控制器应用于冲击波超压测试系统中， 可自动读取和保存重要工作参数。 在实验室环境下， IP核仿真准确。 通过分析爆炸场试验中获得的有效数据， 可以看出该IP核具有很高的可靠性。

FPGA； IIC总线； IP核； 测试系统

HUANG Xiao-min, ZHANG Zhi-jie. Design of IP core for IIC bus controller based on FPGA . Journal of Measurement Science and Instrumentation, 2015, 6(1): 13-18.

10.3969/j.issn.1674-8042.2015.01.003

HUANG Xiao-min (937420530@qq.com)

1674-8042(2015)01-0013-06 doi： 10.3969/j.issn.1674-8042.2015.01.003

Received date： 2014-09-15

CLD number： TP274 Document code： A