Lei Shi, Zhen Huang, Xuefeng Feng

Abstract: A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception.Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays (FPGA) resource consumption and parameter estimation accuracy.

Keywords: digital channelized receiver; field programmable gate arrays (FPGA); non-cooperative;pulse interception

1 Introduction

Digital channelized receivers are widely used in modern electronic intelligence (ELINT) support systems for their high sensitivity and the ability to separate simultaneously arrived signals. Intercepting radar signals and estimating their pulse parameters are important functions of ELINT receivers. A typical digital channelized ELINT receiver is mainly consist of the following parts: the analog front end, the analog-to-digital converter(ADC), digital filter banks and pulse descriptor word (PDW) encoder[1]. With the filter banks,different frequency components of the sampled signal would output from different sub-channels.The followed PDW encoder would then detect and estimate the characteristics of intercepted radar pulses. These characteristics mainly include time of arrival (TOA), pulse width (PW),pulse amplitude (PA), signal frequency and intra-pulse modulation[1].

For non-cooperative signals, their frequency and bandwidth distributions are usually unknown. Limited by the design constraints of the filter bank, it is difficult for channelized receivers to completely intercept the signals with random frequency distribution. One approach to deal with this issue is to divide the channels nonuniformly. However, these non-uniform channelized structures usually have complex structures and require prior knowledge of signals[2−4], which limit their applications in ELINT receivers. For ELINT receivers, the PDW encoders are usually specially designed to meet the requirement of adaptive processing. James Tsui has done extensive research on wideband ELINT receivers and their PDW encoders[1]. In [5], a non-coherent integration method with multiple lengths is utilized to raise the detection sensitivity. In addition, in order to improve the adaptability to signals with different bandwidth, the PDW encoders are divided into in-channel processing and in-block processing[5]. Cheng studied ELINT receivers with different fast Fourier transform(FFT) frame sizes[6], which can be regard as a kind of coherent integration method. Algorithms of combining and eliminating PDWs generated by different FFT channels are also studied in [6].The confliction between leaking-alarms and crosstalks, which caused by the channel overlap design, was studied in [7].

In particular, compared with the uniform channelization method, the computation burden of these adaptive channelization methods might increase intensively. Therefore, how to realize digital channelization efficiently is still a research emphasis. As a part of multi-rate signal processing[8], the basic principle of digital channelization has been studied in detail. Fields and Zahirniak studied the efficient implementation of digital channelization structure based on discrete Fourier transform (DFT)[9]. Based on the weighted overlap-add (WOLA) method proposed in [10], Wang studied the digital channelized structure with WOLA filter banks[11]. Compared with DFT filter banks, there are no integer multiple limitations between the decimation factors and channel numbers for WOLA filter banks. From the perspective of hardware realtime processing, [12] has done in-depth research on FFT-based channelization structure and its implementation on FPGA platforms. In [13−15],Xu realized high performance channelization structures by the parallel designs of multi-FPGAs.George and Chen explored the implementation of FFT-based digital wideband receivers on graphics processing units (GPU)[16].

Despite these efforts, the processing of crosschannel signals is always harder than in-channel processing. Therefore, it is a worthwhile effort to increase the probability that the signal can be completely intercepted by a single sub-channel.An intuitive approach is to process the intercepted signals with densely overlapped channel partitioning at the same time. However, this method might require a large amount of computation.In this paper, an efficient partial sharing digital channelization structure with odd and even stacking is presented. Compared with traditional single stacking mode channelized structure, the sub-channel number of proposed structure is increased by twice while the computation burden is increased by only a fraction.

The contribution of this paper is mainly two folds. Firstly, through the special design of WOLA channelized structure, some parts of filter banks can be shared, which reduces the resource consumption compared with the directly implemented channelization structure. The proposed efficient channelized structure is implemented on the FPGA platform. Its resource utilization is also evaluated, which shows the effectiveness of the partial sharing design. Secondly, the measurement accuracy of pulse parameters, especially TOA, can be improved through the joint usage of odd and even channels. For the conventional single stacking mode channelization structure, the parameter estimation accuracy of crosschannel signals might be poor. By introducing channel arbitration logic, the proposed channelized receiver can process wideband signals with densely overlapped channels. The cross-channel signals of one stacking mode channel can be completely intercepted by the other stacking mode channels. In this way, the measurement accuracy might be improved. Simulations that corroborate the theoretical analysis are also conducted in this paper.

This paper is organized as follows. Section 1 presents the efficient WOLA structure with odd and even stacking. The FPGA implementation of proposed structure is also presented in Section 2.Corresponding performance evaluation is presented in Section 3. Section 4 concludes this paper.

2 Partial Sharing Channelization Structure

2.1 WOLA Channelization Structure with Odd and Even Stacking

With digital channelization, the wideband signal is divided into several sub-band signals. The processing logic of each sub-channel can be realized intuitively by a digital down converter and a low-pass decimation filter. However, this perchannel approach is resource intensive. WOLA structure is an efficient and mathematically equivalent implementation of this per-channel approach. The filters and frequency converters of these channels can be replaced by a weighted overlap-add structure followed by FFT, which reduces the computation burden.

To avoid frequency blind spots, adjacent channels of ELINT receivers are often overlapped with each other. The adjacent channels are usually designed to overlap by 50%[1]. Denote the number of channels asK, the decimation factor asD. The pass-band boundary frequency and stop-band boundary frequency are designed to be π /Kand 2π/K. As shown in Fig.1,channelized structures can be divided into even stacking and odd stacking according to their different channel center frequencies.

Fig.1 Frequency distribution with different stacking modes

In this paper, odd and even stacking is utilized simultaneously. The frequency centers of even stacking channels are the overlap parts of odd stacking channels and vice versa. For a signal whose bandwidth is less than 1 /2 of the channel bandwidth, it can be guaranteed to be completely intercepted by one of the odd and even channels. In this way, the probability of intercepting in-channel signals is increased.

For even stacking channels, themth output ofkth channel is

Define that

For odd stacking channels, the output ofkth channel is

Applying the same principles, letr=i−mD,then

Define that

As noted in [10], we denote the whole digital channelization procedure as four steps: weight,overlap-add, FFT and phase correction.

Herein, the efficient channelization structure that odd and even stacking coexists is shown in Fig.2. For convenience, in this figure, we assume that the length of low-pass filterL=4K. As can be seen from Fig.2, the weight and overlap-add operation can be shared by even stacking channels and odd stacking channels. With this property, the computation burden might be greatly reduced.

Fig.2 Efficient channelization structure with even and odd channel coexisting

In addition, when the computation resources are limited and only one channel stacking mode can be realized, this structure can be implemented with stacking modes fast switching.To change the channel stacking modes, only the symbols in overlap-add step and phase correction values need to be changed.

2.2 Channel Arbitration Logic

The channelization blind spots can be avoided by the overlap design of adjacent channels[9].However, these approaches would introduce the cross-talk problems. Compared with the uniform channelization method, the cross-talk problem is more pronounced in the design of odd and even channels co-existing. Moreover, for the pulsed signals, their rising edges are usually steep, which might produce the rabbit ear effect[1].

In view of the above problems, the following steps are adopted to reduce the influence of cross-talk. The intercepted pulses can be divided into in-channel pulses and cross-channel pulses according to their bandwidths[5]. For cross-channel pulses, whose bandwidth is greater than the channel bandwidth, the outputs of all channel PDW encoders are selected. For in-channel pulses, the output PDWs of adjacent channels would be selected by TOA, PA and signal frequency. When the arrival times and frequencies of the pulses are close, the pulse with large amplitude would be selected as the final output.Moreover, the PDWs that caused by the rabbit ear effect were removed by setting the minimum pulse width.

3 Performance Evaluation

In this section, the improvements over traditional methods of proposed structure in terms of FPGA resource consumption and parameter measurement accuracy are evaluated through experiments and simulations. Corresponding analysis is also conducted in this section.

3.1 FPGA Resource Consumption

The channelized structure of this paper is implemented on Xilinx’s Virtex-7 FPGA, whose specific part number is XC7VX690T. In this paper, the output of ADC is complex signal of 1.25 GSPS(Gbit/s). Channel numberK=32, and the decimation factorD=8. Therefore, the sampling rate and bandwidth of each channel is 156.25 MHz and 39.062 5 MHz respectively. The order of the prototype low-pass filterL=256. The resource consumptions of the whole channelized structure are evaluated in terms of digital signal processors (DSPs), slice lookup tables (LUTs) and slice registers.

In order to realize real-time processing, a full parallel pipeline 32-point FFT structure is implemented on FPGA. This FFT structure processes 32 complex input signals in parallel. By using decimation in time (DIT), the 32-point FFT is decomposed into eight 4-point FFTs. Since the 4-point FFT can be realized without complex multiplication, the main consumption of multiplier comes from the radix-2 butterfly operations and the radix-4 butterfly operations.

For channel with odd stacking, it is necessary to perform the phase correction operation before and after FFT operation. For channel with even stacking, phase correction is only required after FFT operation. SinceK/D=4, which is a special design of this paper, the phase correction operations of even stacking channels can be realized without multiplier.

The multiply-add operation takes a large proportion of all operations. In this paper, this operation is implemented by DSPs. Moreover,the usage of distribute arithmetic (DA) can reduce the consumptions of valuable DSPs, although it might increase the consumptions of slice LUTs, slice registers and block RAMs.

We denote the proposed weight-sharing structure as efficient structure and the WOLA structure in [11] as direct structure. Fig.3 and Fig.4 depict the schematic diagrams for direct structure and efficient structure. Even stacking channels and odd stacking channels are both implemented for these two structures. The FPGA resource consumptions of different channelization structures are shown in Fig.5. As can be seen in Fig.5, for the proposed efficient channelized structure with even and odd channel co-existing, the resource consumption has not doubled with the number of channels. In addition, the decrease of DSPs’ consumption is the largest, which proves that the sharing of weighted filters is the main reason for reducing resource consumption.

Fig.3 Schematic diagram for direct structure

Fig.4 Schematic diagram for efficient structure

Fig.5 FPGA resource consumptions

3.2 Parameter Measurement Accuracy

The measurement of pulse parameters is an important function of channelized receiver. Among them, the measurement of TOA has certain particularity. For example, in the application of passive localization, the localization accuracy is directly affected by the measurement accuracy of TOA[17].

The input signals in the simulation are two pulses with a constant pulse repetition interval(PRI). The intra-pulse waveforms of these two pulses are the same, which are linear frequency modulated (LFM) signals with bandwidth of 60 MHz. The starting frequency of the LFM signal is 556.875 MHz. The PRI and PW are set to be 7.5 μs and 5 μs respectively. The signal noise ratio (SNR) of input signal is set to 6 dB. The pulse edge is processed by a square-root raised cosine roll-off filter, and the width of pulse rising edge is 16 ns. The time domain output waveforms of digital channelizers are shown in Fig.6.

Fig.6 Channel output waveforms

Given that the bandwidth of input signal is greater than the bandwidth of a sub-channel in this paper, the generation of cross-channel pulses is inevitable. As shown in Fig.6, the number of cross-channel pulses varies with the stacking modes of filter banks. The cross-channel pulse number of even channels is smaller than that of odd channels. Since the start frequency of LFM pulse is near to the overlap part of odd stacking channels, the amplitude of pulse head in odd stacking channels is smaller than that in even stacking channels. In addition, Fig.6 also depicts that the channelized structure can improve the sensitivity since that the sub-channel bandwidth is smaller than the input bandwidth.

Fig.7 depicts the influence of different stacking modes on TOA measurement accuracy under the scenario above. In the simulation,TOA is measured by envelope detection. As shown in Fig.7, under low SNR, even stacking channels have better parameter measurement accuracy than odd stacking channels in the above simulation scenes. But for pulses whose starting frequency near to the overlap parts of even stacking channels, odd channels are more advantageous. For non-cooperative emitters, the frequency distribution is unknown and random. Therefore,it would be more advantageous to use both odd and even stacking channels than to use only one channel stacking mode.

Fig.7 TOA measurement accuracy versus SNR

4 Conclusion

An efficient partial sharing channelization structure with odd and even stacking modes co-existing is discussed in this paper. Compared with the single stacking mode approach, the proposed structure has better TOA measurement accuracy since it has densely overlapped channels. Compared with the traditional directly implemented channelization structure, the proposed structure requires less computation because of the special partial sharing design. A practical design example is given in this paper. FPGA resource consumptions and TOA measurement accuracy corresponding to the given design example are evaluated, which validates the advantages of the proposed structure. In addition, we notice that the proposed structure also provides a potential approach for fast switching channel stacking modes,which might have some interesting uses and would be studied in the near future.