JU Qian-Kun HONG Wen-Ting LIU Wei,

Grain Boundary Effects on the Mobility of Chemical Vapor Deposition Synthesized Monolayer MoS2-FETs①

JU Qian-Kuna,bHONG Wen-Tinga,bLIU Weia,b,c②

a(350002)b(100049)c(350108)

Molybdenum disulphide (MoS2) has emerged as a promising candidate for low-power digital applications.However, grain boundaries play a decisive role in determining the carrier mobility and performance of MoS2-FETs.In this work, we report a systematic study on the grain boundary of chemical vapor deposition (CVD) MoS2.We found that in the ON-state, if current flows across a grain boundary that is aligned perpendicular to the channel length, the current of CVD MoS2-FETs can be significantly reduced, while in the OFF-state, the effect is negligible.Metal-insulator-transition is clearly observed, indicating the high quality of our CVD samples, and it is also shown that grain boundaries increase the metal-insulator-transition crossover-voltage in MoS2-FETs.Thereby, this work provides useful information and guidance in understanding the nature of carrier transport in synthesized MoS2devices, and the developed framework can be applied to other 2semiconductors in general, as well as in optimizing the CVD process and device design with 2materials.

grain boundary, golybdenum disulfide, ghemical vapor deposition, field-effect transistor;

1 INTRODUCTION

Atomically-thin molybdenum disulphide (MoS2) has emerged as a promising candidate for low-power digital applications[1-7].The development of chemical vapor deposition (CVD) technology in the synthesis of large-area monolayer MoS2enables the possibility of fabricating entire digital circuits and systems on MoS2[8-15].However, the current synthesis techniques can only grow individual MoS2domains or polycrystalline MoS2films on dielectric substrates[8-15].If grain boundaries exist in the channel of a field-effect transistor (FET), the imperfection sites will induce extra scattering, thereby causing variations in the device performance.Hence, grain boundary effects on the electrical properties of MoS2film can not be ignored.Although the effects of grain boundaries on the performance of CVD MoS2-FETs have been noticed in few works[14-16],there is a lack of comprehensive study of grain boundary effects on the performance of CVD monolayer MoS2-FETs.Recently, Ly et al.observed misorientation-angle-dependent electrical property of CVD MoS2film[17].However, since a grain boundary may consist of many types of orientations (or angles), it is desirable to study the mechanism of grain boundary effects on the carrier transport in high-quality MoS2samples.This study will be helpful in optimizing the design and performance of MoS2for nanoscale electronic and optoelectronic devices.Such study is also critical for optimizing the CVD process for emerging 2materials including MoS2.In this paper, combining abinitio theoretical calculations with carefully designed experiments, we report a systematic approach to understand grain boundary effects on the performance of monolayer MoS2-FETs on CVD synthesi-zed high-quality samples.

Fig.1.(a) Sideand top views of the schematic of a prototype hybrid grain boundary between two monolayer MoS2films.In this example, the GB consists of zigzag and armchair geometries.(b) Sideand top views of the schematic of a stacked GB formed between two monolayer MoS2films.The two pieces of MoS2climb over each other during the growth

In general, there are two types of grain boundaries found in the CVD synthesized MoS2films, as shown in Fig.1.In large MoS2films, stacked grain boundaries are more common than hybrid grain boundaries (indicated by the red arrows in Fig.2a).However, in CVD individual domains, the hybrid grain boundary can be distinguished by the shape and orientation of the edge of MoS2domains.Once the individual domains merged into an entire MoS2film, hybrid grain boundaries can not be easily distinguished, while stacked grain boundaries can be easily avoided for device fabrication due to the distinct optical contrast.Then, hybrid grain boundaries may influence the performance of MoS2devices.Hence, in this work, device fabrication and theoretical calculations are performed based on the hybrid grain boundary to accurately collect the information of grain boundary effect on the carrier transport.

Fig.2.(a) Low magnification optical microscope image of the monolayer MoS2film synthesized by CVD.Dark dots and lines indicate the grain boundaries, which are indicated by the red arrows.Inset shows a large magnification optical microscope image.Dark lines are stacked grain boundaries.(b) High magnification optical microscope image of the individual domains.The grain boundaries are illustrated by the red dash lines.(c) AFM image near the grain boundary.The red dotted line identifies the grain boundary.(d)The AFM line height profile along the direction of the white arrow in Fig.2(c), indicating that the sample thickness is 0.75 nm.At the same time, a significant decrease in the thickness at the grain boundaries was observed.(e) Raman spectra of our synthesized monolayer MoS2.Raman laser wavelength: 633 nm.2LA(M) is a second-order Raman mode due to LA phonons at the M point in the Brillouin zone.(f) Photoluminescence spectra of monolayer CVD MoS2

2 EXPERIMENTAL

2.1 CVD synthesis of MoS2 monolayer

In this work, monolayer (1L) MoS2is grown by vapor transport synthesis from solid powder precursors.High purity MoO3(99.5%, 5 mg) powder and SiO2(280 nm)/Si wafer as the growth substrate were placed in separate alumina boats and were loaded in the center of a 2 indiameter quartz-tube furnace.The boat with sulfur (≥99.5%, 200 mg) powder was placed 20 cm away from the center of the tube furnace.For the MoS2monolayer growth, the center of the furnace was heated to 750 ℃ for 10 min with the flow of 200 sccm Ar.After growth, the system was cooled down to room temperature while flowing with 500 sccm Ar.Fig.2a is the low magnification optical microscope image of monolayer MoS2film synthesized by CVD.Dark dots and lines indicate the grain boundaries, which are indicated by the red arrows.Inset shows a large magnification optical microscope image.The grain boundaries are also marked by the red dashed lines on the individual monolayer MoS2grains in Fig.2b.The shape of CVD grown MoS2is determined by the ratio of the molybdenum atoms over Sulphur atoms on the deposition site[18].If the Mo:S ratio is not equal to 1:1, the shape of CVD grown MoS2is triangular[18].The thickness can be evaluated through Raman spectroscopy by the peak positions of2g1and1gand the ratio of2g1over1gas shown in Fig.2c[12].Fig.2d shows the photoluminescence spectra of monolayer MoS2.There is a sharp peak around 1.8 eV, which is consistent with the fact that the bandgap of monolayer MoS2is 1.8 eV[19].

2.2 Device fabrication of MoS2-FET

For the device fabrication, synthesized MoS2films are transferred onto 90 nm SiO2/Si substrate.The shapes of MoS2(Fig.3a～3c) were defined by electron-beam lithography followed by an 80 seconds XeF2etching.First, a layer of MMA copolymer was spin-coated on a SiO2(90 nm)/Si (++) substrate carrying MoS2samples, and then baked on a heating table at 120 ℃ for 2 minutes.After that, another layer of PMMA was spin coated on the substrate, and then baked at 120 ℃ for 10 minutes.The drain and source are defined by electron beam lithography.After the conventional development process, a Ti/Au metal layer (Ti: 10 nm, Au: 100 nm) is deposited by electron beam evaporation to form a source-drain electrode.Finally, acetone is used for the stripping process.

Fig.3.Device fabrication flow.(a) Selection of grain boundary using optical microscope.White dashed lines show the GBs.(b) MoS2ribbons are defined by electron-beam lithography.Red lines indicate the MoS2ribbons which are perpendicular to the GBs.(c) MoS2was etched by XeF2for 80 seconds.The purple area is the remaining MoS2after XeF2etching.(d) Optical microscope images of fabricated MoS2FET with Ti contact on SiO2(90 nm)/Si (++).Ti (10 nm) and Au (100 nm) are used as contact metals

2.3 Characterization

The thickness of MoS2film is identified using optical microscope and AFM (Fig.2a～2d), indicating that the sample thickness is 0.75 nm.At the same time, a significant decrease in the thickness at the grain boundaries was observed.Raman spectra are depicted in Fig.2e and photoluminescence spectra in Fig.2f.Fig.4 shows the detailed information of our back-gated monolayer MoS2-FET device fabrication.The source and drain contacts are Ti/Au (10 nm/100 nm) deposited by electron beam evaporation.For four point measurements, current () flows from1 to4, and the voltages are measured on2 and3.Hence, channel resistance can be extracted as (2-3)/.All of the devices are annealed at 5 × 10-6mbar, 420 K for 2 hours to reduce contact resistance and remove absorbed moisture.All the measurements are carried out at room temperature.Before annealing, MoS2-Ti contact showed clear Schottky contact behavior.After annealing, MoS2-Ti contact exhibits an ohmic contact confirmed by the linear behavior ofI-Vcurves, as shown in Fig.4b and 4d, respectively.The devices compared in this work are fabricated on the same MoS2flakes to reduce variations.All GBs in this work are designed perpendicular to the current flow direction to study the worst-case situation.

3 RESULTS AND DISCUSSION

Figs.4a and 4c show the transfer curves of back-gated MoS2-FETs.They clearly display-type behavior, which is consistent with most of CVD MoS2FETs.The ON/OFF ratios of the two types of MoS2-FETs are in the range of 107～108, which is comparable to the MoS2-FETs fabricated on exfoliated samples[19].However, the ON-current is lower than that of FETs fabricated on exfoliated natural MoS2samples because of the doping effect[19].The natural MoS2is usually doped by various halogen elements, resulting in an n type doping effect.Compared with the natural MoS2sample, CVD synthesized MoS2has less dopants because of using high purity sulphur and MoO3.Hence, the CVD MoS2has less impurities, which leads to a high carrier mobility and low current.As shown in Fig.4b, d, both sets of theI-Vcurves of MoS2-FETs display linear behavior, indicating that the contact is nearly ohmic in nature.It has been shown that Ti can transfer electron to a clean MoS2surface to form a nearly ohmic contact.However, the MoS2-FET without grain boundary in the channel displays a 30% larger ON-current than that of the MoS2-FET with a grain boundary in the channel (Figs.4b and 4d).

Fig.4.I-Vcurves of monolayer MoS2-FET with current plotted in both linear (left) and logarithmic (right) scales (a) without GB (w/o GB) in the channel and (c) with GB in the channel.(b), (d) correspondingI-Vcurves of (a) and (c), respectively

The ON-current is 23.5 µA/µm (V= 8 V,V= 30 V) on the long channel (= 8 µm) back-gated MoS2-FET without a grain boundary (Fig.4b).However, the ON-current ofFET (= 8 µm) with a grain boundary in the channel is reduced to 15.2 µA/µm (V= 8 V,V= 30 V), as shown in Fig.4d and Fig.5a, indicating that the grain boundary can significantly reduce the ON-current by introducing extra scatterings.On the other hand, from our analysis of many devices, no clear evidence of grain boundary influence on the OFF-current could be identified (Fig.5b).This is likely due to the fact that the OFF-current levels of all our devices are very low–in the range of 10-12to 10-14A.

Fig.5.(a) Ids-Vbg curves of MoS2-FET without GB (solid lines) and with GB (dashed lines).(b) Statistics of the OFF-current of the MoS2-FETs

Fig.6 shows the temperature dependent current of a device as a function of back gate voltage.Without influence of grain boundary, MoS2FETs show a clear metal-insulator transition (MIT) like behavior[21].Note that most of the MIT characteristics have been observed on exfoliated samples.Hence, the observation of MIT phenomenon on our CVD sample indicates that our CVD sample has high quality.WhenV< 18 V, monolayer MoS2behaves as a classical semiconductor with conductance increasing with temperature rise due to the increased thermal generation of carriers.ForV> 18 V, the conductance decreases with increasing temperature, indicating metallic behavior (Fig.6a).For MoS2with grain boundary in the channel, this crossover point occurs at higherV(V> 26 V, Fig.6b), because the grain boundary has greater impact on the carrier transport at low temperature, which leads to the faster decrease of the current at low temperature with respect to the high temperature condition.

Fig.6.Current as a function of gate voltage for different temperature.(a) Without grain boundary in the channel, (b) With grain boundary influence.MoS2-FETs exhibit a clear MIT behavior.WhenV< 18 V, monolayer MoS2behaves like a semiconductor with conductance increasing with temperature.ForV> 18 V, the conductance decreases with increasing temperature, indicating metallic behavior.For MoS2with grain boundary in the channel, this crossover point occurs at higherV(V> 26 V, Fig.6b).V= 1V for both plots

The field effect mobility of MoS2can be extracted as=(/)/dVC-1.At 310 K, our synthesized long channel (= 8 µm) MoS2-FET without a grain boundary shows high quality with a mobility of 33.8 cm-2/V×s which is higher than most reported values[5-7,22].However, in a long channel device (= 8 µm) with a GB, the mobility of the device decreases to 19.9 cm-2/V×s (Fig.7a).The plot of the mobility as a function of temperature reveals that grain boundary can significantly reduce the mobility.Besides impurity and phonon scattering, grain boundary is another factor contri-buting to the mobility degradation and is rather significant.This point has also been confirmed by the analysis of the temperature dependence of the mobility damping factor(～-ɤ), as shown in Fig.7b.Above 100 K, mobility damps with a power law with a temperature dependence of～-ɤ.With grain boundary, MoS2-FET displays a lagerfactor of 2.4 than that of MoS2-FET without grain boundary, indicating that grain boundary can induce extra scattering to further reduce the mobility.

Fig.7.(a) Channel conductance () of MoS2-FET without grain boundary (black line), and with grain boundary (red line) measured at 310 K by 4-probe method.(b) Intrinsic mobility of MoS2of FETs without grain boundary (blue), and with grain boundary (red line) as a function of temperature

4 CONCLUSION

In summary, in this paper, we report the first systematic study of the effects of hybrid grain boundaries on the performance of CVD synthesized monolayer MoS2-FETs.Our results reveal that grain boundaries play a decisive role in determining the carrier mobility and performance of MoS2-FETs.In the ON-state, if current flows across a grain boundary that is aligned perpendicular to the channel length, the current can be significantly reduced, while in the OFF-state, the effect is negligible.Metal-insulator-transition is clearly observed, indicating the high quality of our CVD samples, and it is also shown that grain boundaries increase the metal-insulator-transition crossover-voltage in MoS2-FETs.Thereby, this work provides useful information and guidance in understanding the nature of carrier transport in synthesized MoS2devices, and the developed framework can be applied to other 2semiconductors in general, as well as in optimizing the CVD process and device design with 2materials.

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3 July 2020;

1 September 2020

① This work was supported by the National Natural Science Foundation of China (No.61674152)

.E-mail: liuw@fjirsm.ac.cn

10.14102/j.cnki.0254–5861.2011–2934