流水线式LDPC译码器的FPGA设计与仿真
2014-11-07单元旭崔闻
单元旭+崔闻
摘 要: LDPC码在深空通信中有很好的实用价值,同时LDPC码也被广泛应用于光纤通信、卫星数字视频和音频广播等领域。针对LDPC译码器提出一种新的设计思路,将流水线思想从译码算法本身扩展到译码器的整体设计中,设计出可以多帧并行且结构简单的译码器,最后从吞吐量和资源消耗两方面进行仿真验证。
关键词: LDPC; 译码器; 流水线; FPGA
中图分类号: TN91?34 文献标识码: A 文章编号: 1004?373X(2014)21?0015?04
Design and simulation of pipeline style LDPC decoder based on FPGA
SHAN Yuan?xu, CUI Wen
(School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin 150001, China)
Abstract: LDPC code in deep space communication has very good practical value, and has been widely used in optical fiber communication, satellite digital video and audio broadcasting. A new method to design LDPC decoder is proposed. The idea of pipeline is abstracted from decoding algorithm and applied to the overall design of decoder. Based on this method, a decoder with simple structure, which can process multiple parallel frames, was designed. Its throughput and resource consumption were verified by simulation.
Keywords: LDPC; decoder; pipeline; FPGA
0 引 言
LDPC码已被广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域[1]。在加性高斯白噪声信道环境下,BPSK调制时,归一化最小和译码算法能很好地平衡译码性能和算法复杂度,易于硬件实现[2],且常以流水线的形式出现在译码器的设计中。本文针对LDPC译码器提出一种新的设计思路,将流水线思想应用到译码器的整体设计中,设计出可以多帧并行且结构简单的译码器,最后通过仿真对其性能进行验证。
1 归一化最小和译码算法的流水线化
归一化最小和译码算法分为两步迭代,即变量节点运算(VNP)与校验节点运算(CNP)。
VNP:
[qnm=Pn+m∈M(n)\mrmn] (1)
CNP:
[rmn=n∈N(m)\nsign(qnm)×minn∈N(m)\nqnm×α] (2)
式中:[M(n)]表示[H]矩阵中第n列中1的所有位置;[N(m)]表示[H]矩阵中第m行中1的所有位置;[M(n)\m]表示从[M(n)]中去掉第m行那个1之后的子集;[N(m)\n]表示从[N(m)]中去掉第n列那个1之后的子集;Pn表示第n列对应的接收到的初始电平值;[qnm]表示本次迭代中第n列第m行那个1对应的变量节点运算结果;[rmn]表示本次迭代中第m列第n行那个1对应的校验节点运算结果;[α]为归一化因子。初始化时先进行VNP运算,此时的rmn均为0。……
