刘 燕,王京梅,张 帆,兰中文

摘 要:流量管理芯片的验证是目前业界的热点与难点,验证工程师们一直在努力寻找用于流量测量的较好方法。采用System Verilog 语言,基于Synopsys公司最新推出的验证方法学VMM,提出一种用于流量管理芯片验证的分层次验证环境。该环境对流量测量方法进行重点研究,放弃采用参考模型的传统验证思路,提供一种参考基准可变,时间窗位置可移,长度可调的,可在不同设计间高度重用的流量检测机制。该验证环境及验证方法在海思半导体某流量管理芯片开发过程中的成功应用,保证了芯片开发质量,缩短了项目开发周期,为其他同类芯片的开发提供了强有力的支持。

关键词:VMM;流量管理;芯片;验证

中图分类号:TN407文献标识码:A

文章编号:1004-373X(2009)12-015-04

Verification of Traffic Managing Chip Based on VMM

LIU Yan1,WANG Jingmei1,ZHANG Fan2,LAN Zhongwen1

(1.State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China,Chengdu,610054,China;

2.Hisilicon Technologies Co.Ltd.,Shenzhen,518129,China)

Abstract:The verification of traffic managing chip is currently the hotspot and difficulty in this field.Verification engineers have been trying their best to find a better way to traffic measurement.Adopting System Verilog,based on VMM library supplied by Synopsys,one layered verification environment is presented.Focusing on the research of traffic measurement,abandoning the traditional verification thought with RM,the environment provides one traffic check mechanism,in which reference benchmark is variable,time window is movable and time length is adjustable.Successful application of the verification environment and methods introduced in this article in traffic managing chip in Hisilicon not only shorten the period and assure the quality but also strongly supportd the development of congeneric chips.

Keywords:VMM;traffic managing;chip;verification

0 引 言

随着半导体集成技术的飞速发展,SoC的集成规模日益庞大,集成功能日益复杂。芯片验证在芯片研发中所占的比例越来越重,占据了整个研发周期的70%以上[1]。芯片验证已成为整个芯片流程中的瓶颈,验证的完备性和验证效率的提高成为验证的难点,也是目前验证的主要研究方向。

Synopsys是实现高复杂的SoC设计。最新推出VMM验证方法学[2],基于System Verilog语言。System Verilog具有面向对象语言的抽象数据结构[3],相对于E语言、TCL、C/C++等验证语言,System Verilog的特殊性在于它将设计和验证组合成同一种语言[4],从而使环境实现更加简单,结构更清晰,维护性更强。VMM以其清晰的分层架构体系,便于维护和扩展的优势越来越受到各公司的重视。瑞萨科技采用Synopsys的VCS功能验证解决方案开发复杂的SoC,并选定了VMM方法集,用于验证其重要的Super Hyway总线片上互连架构[5]。……